Sensoray 626 Bedienungsanleitung PDF herunterladen (Seite 25)

Sensoray Model 626 Instruction Manual

11. Watchdog/Miscellaneous Registers

Table 19 Write to MISC1 88 (hex)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

1=Write enable Not used Not used EDCAP

(See P 11)

Not Used Not Used

Not Used

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Not Used Not Used Not Used Not Used Not Used Not Used Not Used Not Used

Table 20 Read from MISC1 88 (hex)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

1=Write

Enabled

1=Watchdog

Timed out

Internal Register EDCAP

(See P 11)

Internal Register Internal Register Internal Register Internal Register

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

Internal Register Internal Register Internal Register Internal Register Internal Register Internal Register Internal Register Internal Register

Table 21 Write to MISC2 90 (hex)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

0= Digital

output 5

0= Digital

output 4

1=Clear

watchdog

1=Charge

Enable

Not used Not used Not used Not used

1=Counter 5

Overflow

1=Counter 4

Overflow

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

0= Digital

output 3

0= Digital

output 2

0= Digital

output 1

0= Digital

output 0

1= Counter 3

Overflow

1= Counter 2

Overflow

1= Counter 1

Overflow

1= Counter 0

Overflow

1=Backup Battery

Enabled

1=Watchdog

Enabled

Watchdog period selection

00=

second

01=

second

10=1 second

11=10 seconds

Table 22 Read from MISC2 92 (hex)

Bit 15 Bit 14 Bit 13 Bit 12 Bit 11 Bit 10 Bit 9 Bit 8

COINT2B COINT2A COINT1B COINT1A COINT0B COINT0A INDINT2B INDINT2A

Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0

INDINT1B INDINT1A INDINT0B INDINT0A 1=Backup Battery

Enabled

1=Watchdog

enabled

Watchdog period selection

00=

second

01=

second

10=1 second

11=10 seconds

The grayed bits do not read back the same registers.

11.1 Battery Charging

Bit 14 “Charge Enable” of MISC2 (92 hex) turns the trickle charging of an optional external backup

battery on and off. The system will default to “Charging off” after a reset.

Before writing to any of the bits of MISC2, except bit 15 (Clear watchdog), the write enable (bit 15) of

MISC1 must be set. This is to prevent accidental modification of the watchdog settings by a crashed

CPU. It is a good idea to clear this bit immediately after writing to MISC2.

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